The present invention relates generally to a nonvolatile latch circuit, and more particularly to a nonvolatile latch circuit for enhanced system performance by storing in a non-volatile way many kinds of states generated during the system operations so that the stored non-volatile data are available to restore the system to the previous state in a case of re-booting.
FIG. 1 is a graph showing the power consumption pattern of a conventional chip as the chip's design rule (or “the technology node”) generally indicative of the chip's integration density shrinks from 180 nm to 65 nm.
Referring to FIG. 1, when the technology node, which indicates the design rule of a conventional device is large (e.g., near the 180 nm technology node), the current consumption of an active current which is an operating current of System On a Chip (SOC) is expected to be larger than the current consumed by the device during a standby mode, i.e., the non-active state.
As the device size becomes smaller or the technology node as in FIG. 1 is scanned from 180 nm to 65 nm, the rising slop of the active current required is rather slow or gradual; however, the slope of the standby current drastically and abruptly increases at about 90 nm. This leads to the drastic increase of the leakage current component of the sub-threshold voltage Vt, which is a constituent of the non-switching current more drastic than the increase of the switching current, which is a main component of the active current. That is, as a device becomes smaller, the proportion of the current consumption in the standby mode is expected to significantly increase due to the leakage current passing through the CMOSs in the standby state.
Therefore, in the standby mode, finding ways to reduce the power consumption of a chip to limit or minimize the expected large amounts of power supplied to these highly integrated chips is desirable. At this time, the circuit that stores the previous conditions of the circuit and that is able to recall those previous conditions is required in order to recover the previous condition of the circuit before the power source to the circuit is interrupted.
A conventional circuit memorizing the prior state of the circuit when the power is off is a nonvolatile latch circuit shown in FIG. 2.
The conventional nonvolatile latch circuit provides a plurality of inverters IV1˜IV8, NMOS transistor SW1, SW2, and a capacitor 10.
Here, the inverter IV1 is synchronized with the clock CK to invert data D. The latch R1 includes the inverters IV2, IV3 of the latch structure, while being synchronized with the clock/CK to latch the output of the inverter IV1. The inverter IV4 is synchronized with the clock/CK to invert the output of the latch R1. The latch R2 includes the inverter IV5, IV6 of the latch structure and latches the output of the inverter IV4 to output data Q.
In response to the switching signal SS, the NMOS transistors SW1, SW2 selectively connect the latch R1 and the capacitor 10. The capacitor 10 provides a plurality of nonvolatile ferroelectric capacitors FC1˜FC4.
At this time, the nonvolatile ferroelectric capacitors FC1, FC2 store the output of the plate line/PL1 which is inverted by the inverter IV7. And, the nonvolatile ferroelectric capacitors FC3, FC4 store the output of the plate line/PL2 which is inverted by the inverter IV8.
The conventional nonvolatile latch circuit having such a circuit configuration is implemented in each circuit function region within the system on chip in order to store the non-volatile data representative of the turn-on state of the power supply switch when the power switch is turned off. Therefore the data are stored in the capacitor 10 through the additional latch R1, R2 before the power switch is turned off, or the previous data is restored when the power switch is turned on.
The conventional nonvolatile latch circuit as described above stores the state of the latch R1, R2 into the capacitor 10 during a storage unit period in entering the power off mode and restores the data stored in the latch R1, R2 during a recall period when entering the power on mode.
But, such a conventional nonvolatile latch circuit stores the previous data only in a preset power off mode. Therefore, problems arise in that the latch data in the active state is lost in the case when there is an occurrence of an accidental power off state during an active period. The will make recovery of the data impossible.